The present embodiments relate to forming semiconductor circuit wafers and are more particularly directed to locating sub-resolution assist features (“SRAF”) on a mask (or reticle) for use with such wafers.
The history and prevalence of semiconductor devices are well known and have drastically impacted numerous electronic devices. As a result and for the foreseeable future, successful designers constantly are improving the semiconductor fabrication process, and improvements are in numerous areas including device size, fabrication efficiency, and device yield. The present embodiments advance these and other goals by improving the methodology for developing parameters to implement sub-resolution assist features on the masks used to form semiconductor devices.
By way of background and as known in the art, semiconductor devices are sometimes referred to as chips, and each chip is created from a portion of a semiconductor wafer. Typically, each chip is located in a respective area on the wafer referred to as a field. Various fabrication steps are taken to form electric circuits on each field. Some of these steps involve photolithography, whereby a light source is directed toward a mask, and light passes through only portions of the mask because so-called features have been previously formed on the mask so that the light that passes is determined by the location of the features. In other words, an image is projected through the mask based on the location of the features, where in some cases the feature is what blocks the light or in other cases the feature is what passes the light. In either case, typically the light image is further directed to a reduction lens that reduces the size of the image and the reduced image is then projected to a selected field on the wafer, where the field selection is determined by a device known as a stepper. The stepper gets its name because it causes the image to step through different fields on the wafer, that is, once the image is projected to one field on the wafer, the stepper disables the light source, repositions either the mask or the wafer, and then enables the light source so that the same image from the same mask is then directed to a different field on the wafer, and so on for numerous fields. Thus, this process repeats until numerous images of the same type are directed to numerous respective fields on the wafer, with the stepper thereby stepping the image from one field to another on the wafer. As each image reaches a field on the wafer, typically the light reacts with a layer of photoresist that was previously deposited on the wafer. The resulting reacted photoresist layer is then etched to remove the unreacted photoresist, leaving behind structures on the wafer that correspond to the same size and shape as the reduced light that previously was directed through the mask and reducer to the wafer. These remaining wafer structures are also referred to as features and note, therefore, that each feature on the mask causes a corresponding feature on the wafer. However, each feature on the mask is larger in size, typically by some integer multiple (e.g., 2, 4, 5, 10), where the multiplier is removed with respect to the wafer by the reducer lens. For example, in a case where the mask features are four times that desired on the wafer, the reducer lens reduces the size of the light image passing through the mask by a factor of four so that each resulting wafer feature will be one-fourth the size (in all dimensions) of each respective mask feature. In this manner, therefore, limitations on the mask may be at a larger size scale than on the wafer, due to the use of the reducer lens.
Given the use of imaging and masks as discussed above, various aspects of semiconductor design are necessarily limited by constraints of the mask and its related technology. In other words, since the mask defines the image that passes through it and that ultimately dictates the layout of the circuit on the wafer, then limitations of the mask represent limitations of the resultant wafer circuit. For example, it is well known that features on the mask may be made only down to a certain limited width, which as of this writing are typically on the order of 250 nm. Moreover, in developing the location of features on a mask, various designers have developed methodologies that place limits on how closely two neighboring features may be formed. More specifically, it has been determined that if such neighboring features are too closely formed, then the features cannot be resolved optically with conventional light source and mask techniques, causing an undesirable or unacceptable image on the wafer. Such limitations are particularly evident when a desired dimension of a wafer feature is smaller than the wavelength of the light that passes through the mask. In this regard, more recently technology has advanced with the use of two techniques that permit creation of even smaller features, each of which is described below.
One technology used for improving wafer features in smaller circuits is known as a phase-shifting mask. In such a mask, the mask blocks light in certain areas and phase shifts light in other nearby areas typically so that the light passing through these latter areas is 180 degrees out of phase with respect to the areas that pass non-phase shifted light. As a result, there is overlap between the non-phase shifted and phase shifted light, causing light interference that effectively cancels some of the overlapping light and produces a clearer edge for the resulting wafer feature.
Another mask technology used for improving wafer features in smaller circuits is known by various names, such as feature assist, assist features, or sub-resolution assist feature (“SRAF”) where the last connotes that the assisting feature on the mask when used with off-axis illumination contributes to a corresponding wafer feature with greater resolution and printing margin than that otherwise obtainable for a given light wavelength. In any event, those assist features are features that are located on a mask, but a key goal of these features is that there is not a counterpart of the mask assist feature formed on the wafer. More particularly, ideally the mask assist feature is small enough and properly located on the mask so that that the assist feature is not transferred onto the wafer because the wafer features are below the dimensional resolution of the lithography system. However, the assist feature is also large enough so that that it does affect the passage of light and thereby impacts a nearby wafer feature, sometimes referred to in this context as a primary feature and that is formed therefore in response to a primary (non-assist) feature on the mask but is further defined by the light that is manipulated by the assist feature.
In view of the above, with assist (or SRAF) technology comes the complexity of a methodology for locating the assist features on the mask or reticle. Often such a method implements a rule-based computer program that considers various of the circuit attributes and layout dimensions so as to generate parameters that in turn are used to form both primary and assist features on the mask. The present embodiments, however, seek to improve upon such technology by permitting and forming certain assist features preferentially for more critical device features i.e. primary features on the mask, with the ability therefore to enhance the printability of corresponding primary features on the wafer, thereby reducing chip size, permitting greater device density per field, and improving yield for smaller dimension circuits. Various other benefits also may be ascertained by one skilled in the art, based on the remaining discussion set forth below. Thus, the prior art provides drawbacks in its limitations of achieving only certain primary feature definition and minimal wafer feature sizes, while the preferred embodiments improve upon these limitations as demonstrated below.